The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Increasingly many electronic systems, such as server platforms, require ever-growing data transfer rate. Resultantly, longer and lossier customized channel and higher routing density in printed circuit boards (PCBs) and/or semiconductor package substrates are often needed. All these factors aggravate the crosstalk interference among adjacent transmission lines in PCB and/or semiconductor package substrates, such as microstrips.
Present solutions typically include: (1) increase the spacing between two routings, which however is not attractive due to the increase in PCB and/or package substrate area and cost; (2) mitigate far end crosstalk (FEXT) by replacing microstrips with striplines, but this is not doable in many practical designs or adds cost; or (3) add a conductor guard trace between two microstrips, but it requires shorting with at least two ground vias at the end points of the microstrips, which can cause some issues in practical design. With respect to conductor guard trace, grounding may lead to a number of problems. First, the impedance discontinuity caused by ground vias can severely degrade the signaling performance. Because the lowest resonant frequency is determined by the maximum spacing of any two adjacent ground vias, it often requires the maximum spacing to be as small as possible. Second, if there is no ground via placed at the end of routing, the open stub of guard line can also degrade the signaling performance. For example, in package design, grounded shield line can lead to “open-stub line”. Third, the ground vias may also make negative impact on the internal layer signal routings.
Also, many electronic systems have to suppress power supply noises and/or alleviate EMI and electromagnetic compatibility (EMC) issues. Typically, decoupling capacitors are employed to suppress power supply noises. To alleviate EMI/EMC, typically, stitching via on PCB, ferrite bead on cables and/or metallic gasket or enclosure at chassis is employed. Both power supply noises and EMI issues are aggravated by the Cavity Resonant Edge Effects (CREE) in PCBs and packages. Further, if a large number of decoupling capacitors are employed to address the power supply noises, the bill of materials would increase, and the useable surface area of a PCB would decrease, resulting in an increase in cost.